Verilog if case statements

Verilog HDL offers three different if statements

1: if(a>b)
	Out1 = itnt1;
2: if(expression)
	 sentence 1;
	else
	 sentence 2;
3: if (expression1)
	 sentence 1;
	else if (expression2) sentence 2;
	else if (expression3) sentence 3;
	else if (expression4) sentence 4;
	…
	else sentence n;

Conditional statements must be used in a block

Verilog case statement

If sentence only has two branches in general, however case can have multiple branches.

General forms:

1:case(expression) <case branch item> endcase
2:casez(expression) <case branch item> endcase
3:casex(expression) <case branch item> endcase

Example:

case (sig)
	1’bz:		$display(“signal is floating”);
	1’bx:		$display(“signal is unknown”);
	default:  $display(“signal is %b”, sig);
endcase

Casex ignores any bit position containing an X or Z; casez only ignores bit positions with a Z. Verilog literals use the both the ? and z characters to represent the Z state. Using ? to represent a Z state is more descriptive for synthesis to represent don’t care logic.

Example1:

reg[7:0] ir;
casez(ir)
	8’b1???????:instruction1(ir);
	8’b01??????:instruction2 (ir);
	8’b00010???:instruction3(ir);
	8’b000001??:instruction4(ir);
endcase

Example2:

reg[7:0] r,mask;
mask = 8’bx0x0x0x0;
casex(r^mask)
	8’b001100xx:stat1;
	8’b1100xx00:stat2;
	8’b00xx0011:stat3;
	8’bxx001100:stat4;
endcase