Sequential blocks and parallel blocks in Verilog

Sequential block(also known as procedure block)

key words: begin end

The sequential block executes a group of statements (blocking assignment statement) in a sequential manner in which they are specified.

Example:

reg x, y;
reg[1:0] z,w;

initial 
begin
	x = 1’b0;
	y = 1’b1;
	z = {x, y};
	w = {y, x};
end

//exp2
reg x, y;
reg[1:0] z,w;
initial
begin
	x = 1’b0;//done at time 0
	#5 y = 1’b1;//done at time 5
	#10 z = {x, y};//done at time 15
	#20 w = {y, x};//done at time 35
end

Parallel block

Key word: fork join

The parallel block executes a group of statements concurrently as their execution starts at the same simulation time.

Example:

reg x,y;
reg [1:0] z,w;

initial
 fork
	x = 1b’0;//done at time 0
	#5 y = 1b’1;//done at time 5
	#10 z = {x, y};//done at time 10
	#20 w = {y, x};//done at time 20
join

features of blocks

We can combine begin-end and fork-join blocks, name a block, and disable a block.

Example

initial
begin : block1// name a block
	x = 1’b0;
	fork : block2
		#5 y = 1’b1;
		#10 z = {x,y};
	Join
	#20 w = {y,x};
end
endmodule

We can use disable <block name> to stop executing a named block. It is like break in c, but c can only exit the current loop, disable can stop any named block in the design.

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